https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115687
Andrew Waterman <andrew at sifive dot com> changed:
What |Removed |Added
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CC| |andrew at sifive dot com
--- Comment #6 from Andrew Waterman <andrew at sifive dot com> ---
I note MIPS sets TARGET_CONST_ANCHOR to 0x8000, and that architecture's ADDIU
instruction has a 16-bit immediate. RISC-V's ADDI instruction has a 12-bit
immediate, so presumably we should be setting it to 0x800.
