https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114310
--- Comment #9 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The releases/gcc-12 branch has been updated by Jakub Jelinek <ja...@gcc.gnu.org>: https://gcc.gnu.org/g:9f484597028f2b2862bf22003dbae25c24ce5930 commit r12-10515-g9f484597028f2b2862bf22003dbae25c24ce5930 Author: Jakub Jelinek <ja...@redhat.com> Date: Thu Mar 14 14:09:20 2024 +0100 aarch64: Fix TImode __sync_*_compare_and_exchange expansion with LSE [PR114310] The following testcase ICEs with LSE atomics. The problem is that the @atomic_compare_and_swap<mode> expander uses aarch64_reg_or_zero predicate for the desired operand, which is fine, given that for most of the modes and even for TImode in some cases it can handle zero immediate just fine, but the TImode @aarch64_compare_and_swap<mode>_lse just uses register_operand for that operand instead, again intentionally so, because the casp, caspa, caspl and caspal instructions need to use a pair of consecutive registers for the operand and xzr is just one register and we can't just store zero into the link register to emulate pair of zeros. So, the following patch fixes that by forcing the newval operand into a register for the TImode LSE case. 2024-03-14 Jakub Jelinek <ja...@redhat.com> PR target/114310 * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For TImode force newval into a register. * gcc.dg/pr114310.c: New test. (cherry picked from commit 9349aefa1df7ae36714b7b9f426ad46e314892d1)
