[Bug target/115102] [SH] GCC misunderstands swap.b instruction

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115102

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <u...@gcc.gnu.org>:

https://gcc.gnu.org/g:e715204f203d318524ae86f3f2a1e8d5d7cb08dc

commit r15-930-ge715204f203d318524ae86f3f2a1e8d5d7cb08dc
Author: Uros Bizjak <ubiz...@gmail.com>
Date:   Thu May 30 21:27:42 2024 +0200

    i386: Rewrite bswaphi2 handling [PR115102]

    Introduce *bswaphi2 instruction pattern and enable bswaphi2 expander
    also for non-movbe targets.  The testcase:

    unsigned short bswap8 (unsigned short val)
    {
      return ((val & 0xff00) >> 8) | ((val & 0xff) << 8);
    }

    now expands through bswaphi2 named expander.

    Rewrite bswaphi_lowpart insn pattern as bswaphisi2_lowpart in the RTX form
    that combine pass can use to simplify:

    Trying 6, 9, 8 -> 10:
        6: r99:SI=bswap(r103:SI)
        9: {r107:SI=r103:SI&0xffffffffffff0000;clobber flags:CC;}
          REG_DEAD r103:SI
          REG_UNUSED flags:CC
        8: {r106:SI=r99:SI 0>>0x10;clobber flags:CC;}
          REG_DEAD r99:SI
          REG_UNUSED flags:CC
       10: {r104:SI=r106:SI|r107:SI;clobber flags:CC;}
          REG_DEAD r107:SI
          REG_DEAD r106:SI
          REG_UNUSED flags:CC

    Successfully matched this instruction:
    (set (reg:SI 104 [ _8 ])
        (ior:SI (and:SI (reg/v:SI 103 [ val ])
                (const_int -65536 [0xffffffffffff0000]))
            (lshiftrt:SI (bswap:SI (reg/v:SI 103 [ val ]))
                (const_int 16 [0x10]))))
    allowing combination of insns 6, 8, 9 and 10

    when compiling the following testcase:

    unsigned int bswap8 (unsigned int val)
    {
      return (val & 0xffff0000) | ((val & 0xff00) >> 8) | ((val & 0xff) << 8);
    }

    to produce:

            movl    %edi, %eax
            xchgb   %ah, %al
            ret

    The expansion now always goes through a clobberless form of the bswaphi
    instruction.  The instruction is conditionally converted to a rotate at
    peephole2 pass.  This significantly simplifies bswaphisi2_lowpart
    insn pattern attributes.

            PR target/115102

    gcc/ChangeLog:

            * config/i386/i386.md (bswaphi2): Also enable for !TARGET_MOVBE.
            (*bswaphi2): New insn pattern.
            (bswaphisi2_lowpart): Rename from bswaphi_lowpart.  Rewrite
            insn RTX to match the expected form of the combine pass.
            Remove rol{w} alternative and corresponding attributes.
            (bswsaphisi2_lowpart peephole2): New peephole2 pattern to
            conditionally convert bswaphisi2_lowpart to rotlhi3_1_slp.
            (bswapsi2): Update expander for rename.
            (rotlhi3_1_slp splitter): Conditionally split to bswaphi2.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr115102.c: New test.