https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90323
--- Comment #21 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Andrew Pinski from comment #20)
> The aarch64 backend matches this:
> (insn 15 10 16 2 (set (reg/i:V4SI 32 v0)
> (xor:V4SI (and:V4SI (xor:V4SI (reg:V4SI 101)
> (reg:V4SI 102))
> (reg:V4SI 103))
> (reg:V4SI 101))) "/app/example.cpp":7:1 3103
> {aarch64_simd_bslv4si_internal}
>
> for the `bit v0.16b, v1.16b, v2.16b` instruction. which was done r5-6601 (PR
> 64448) .
One thing for the middle-end here is if we have `(xor (and (xor A B) C) B)` we
could try expand it into `(a&c)|(b&~c)` if there is an optab for the &~ (which
I am aiming to add for other reasons). I am not sure if powerpc vsx has &~
though. I will doing my development on both x86_64 and aarch64 and it will be
up to the other targets to add the optab pattern if needed.
