[Bug target/114887] RISC-V: expect M8 but M4 generated with dynamic LMUL for TSVC s319

[juzhe.zhong at rivai dot ai via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114887

--- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
The "vect" cost model analysis:

https://godbolt.org/z/qbqzon8x1

note:   Maximum lmul = 8, At most 40 number of live V_REG at program point 6
for bb 3

It seems that we count one more variable in program point 6 ?