https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114506
--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Demin Han <demin...@gcc.gnu.org>: https://gcc.gnu.org/g:ca2f531cc5db4f1020d4329976610356033e0246 commit r15-47-gca2f531cc5db4f1020d4329976610356033e0246 Author: demin.han <demin....@starfivetech.com> Date: Tue Mar 26 16:52:12 2024 +0800 RISC-V: Refine the condition for add additional vars in RVV cost model The adjacent_dr_p is sufficient and unnecessary condition for contiguous access. So unnecessary live-ranges are added and result in smaller LMUL. This patch uses MEMORY_ACCESS_TYPE as condition and constrains segment load/store. Tested on RV64 and no regression. PR target/114506 gcc/ChangeLog: * config/riscv/riscv-vector-costs.cc (non_contiguous_memory_access_p): Rename (need_additional_vector_vars_p): Rename and refine condition gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/pr114506.c: New test. Signed-off-by: demin.han <demin....@starfivetech.com>
