https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53938
--- Comment #6 from rsaxvc at gmail dot com --- This also impacts Cortex-M0 & M23 on GCC13.2.0, just with the new extension instructions. Oddly, when loading a volatile u8 or u16 on Cortex-M3/4/7 does not generate extra zero extension instructions. But these cores do still have separate ldrb/ldrb + sxtab/sxtah sign extension instead of LDRSB/LDRSH.
