https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810
--- Comment #15 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jakub Jelinek <ja...@gcc.gnu.org>: https://gcc.gnu.org/g:628c2221d38715a64f828e3635317293d150e001 commit r14-10099-g628c2221d38715a64f828e3635317293d150e001 Author: Jakub Jelinek <ja...@redhat.com> Date: Tue Apr 23 23:30:27 2024 +0200 i386: Avoid =&r,r,r andn double-word alternative for ia32 [PR114810] As discussed in the PR, on ia32 with its 8 GPRs, where 1 is always fixed and other 2 often are as well having an alternative which needs 3 double-word registers is just too much for RA. The following patch splits that alternative into two, one with o is used even on ia32, but one with the 3x r is used just for -m64/-mx32. Tried to reduce the testcase further, but it wasn't easily possible. 2024-04-23 Jakub Jelinek <ja...@redhat.com> PR target/114810 * config/i386/i386.md (*andn<dwi>3_doubleword_bmi): Split the =&r,r,ro alternative into =&r,r,r enabled only for x64 and =&r,r,o. * g++.target/i386/pr114810.C: New test.
