[Bug target/114714] New: [RISC-V][RVV] ICE: insn does not satisfy its constraints (postreload)

[schwab--- via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114714

            Bug ID: 114714
           Summary: [RISC-V][RVV] ICE: insn does not satisfy its
                    constraints (postreload)
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: sch...@linux-m68k.org
  Target Milestone: ---
            Target: riscv64-*-*

Created attachment 57945
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57945&action=edit
widen_mul_test.cc.ii

$ c++ -O2 -std=c++17 -fPIE -march=rv64gcv1p0 -S widen_mul_test.cc.ii
../hwy/tests/widen_mul_test.cc: In function 'void
hwy::N_RVV::TestAllReorderWidenMulAccumulate()':
../hwy/tests/widen_mul_test.cc:348:1: error: insn does not satisfy its
constraints:
  348 | }
      | ^
(insn 1205 1214 5405 69 (set (reg:RVVM1SI 97 v1 [orig:687 _1177 ] [687])
        (if_then_else:RVVM1SI (unspec:RVVMF32BI [
                    (const_vector:RVVMF32BI repeat [
                            (const_int 1 [0x1])
                        ])
                    (reg:DI 25 s9 [orig:539 _889 ] [539])
                    (const_int 2 [0x2]) repeated x2
                    (const_int 0 [0])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (zero_extend:RVVM1SI (reg:RVVMF2HI 97 v1 [orig:654 _1100 ] [654]))
            (unspec:RVVM1SI [
                    (reg:DI 0 zero)
                ] UNSPEC_VUNDEF))) "../hwy/ops/rvv-inl.h":1964:386 discrim 1
8360 {pred_zero_extendrvvm1si_vf2}
     (nil))
during RTL pass: postreload
../hwy/tests/widen_mul_test.cc:348:1: internal compiler error: in
extract_constrain_insn, at recog.cc:2713