https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114639
--- Comment #12 from Li Pan <pan2.li at intel dot com> ---
#include <riscv_vector.h>
extern unsigned long get_vl ();
#if 0
#else
vint32m1_t test (vint32m1_t a)
{
unsigned b;
return __riscv_vadd_vx_i32m1 (a, b, get_vl ()); // No ICE
}
vbool16_t test (vuint64m4_t a)
{
unsigned long b;
return __riscv_vmsne_vx_u64m4_b16 (a, b, get_vl ()); // ICE
}
#endif
This is comes from the below parts:
!(targetm.class_likely_spilled_p (REGNO_REG_CLASS (ret_start)));
For RVV, the reg_class values are listed as below. Because the Vector Mask has
only one reg, then it will be considered as likely spilled as the hook
TARGET_CLASS_LIKELY_SPILLED_P default returns true if reg_class_size[class] ==
1.
Not very sure if overriding TARGET_CLASS_LIKELY_SPILLED_P hook for riscv is a
reasonable fix, trying to understand TARGET_CLASS_LIKELY_SPILLED_P...
--------panli-----reg_class_size[0]=0
--------panli-----reg_class_size[1]=14
--------panli-----reg_class_size[2]=26
--------panli-----reg_class_size[3]=32
--------panli-----reg_class_size[4]=32
--------panli-----reg_class_size[5]=2
--------panli-----reg_class_size[6]=1 <= VM
--------panli-----reg_class_size[7]=31 <= VD
--------panli-----reg_class_size[8]=32 <= V
--------panli-----reg_class_size[9]=98
