[Bug middle-end/114069] Type punning RISC-V and SVE vectors causes ICE at -O1

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114069

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|Type punning RISC-V vectors |Type punning RISC-V and SVE
                   |causes ICE at -O1           |vectors causes ICE at -O1
   Last reconfirmed|                            |2024-02-24
           Keywords|                            |ice-on-valid-code
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1
             Target|riscv                       |riscv aarch64
          Component|target                      |middle-end

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.

This is not only a RISCV issue but also happens with aarch64's SVE types too:
```
#include <arm_sve.h>

svint8_t f(svuint8x2_t s) {
        return *reinterpret_cast<svint8_t*>(&s);
}

```