https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112375
--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Tamar Christina <tnfch...@gcc.gnu.org>: https://gcc.gnu.org/g:7d8585c0c0e5934780281abdee256ae6553e56e8 commit r14-9137-g7d8585c0c0e5934780281abdee256ae6553e56e8 Author: Tamar Christina <tamar.christ...@arm.com> Date: Thu Feb 22 15:32:08 2024 +0000 AArch64: update vget_set_lane_1.c test output In the vget_set_lane_1.c test the following entries now generate a zip1 instead of an INS BUILD_TEST (float32x2_t, float32x2_t, , , f32, 1, 0) BUILD_TEST (int32x2_t, int32x2_t, , , s32, 1, 0) BUILD_TEST (uint32x2_t, uint32x2_t, , , u32, 1, 0) This is because the non-Q variant for indices 0 and 1 are just shuffling values. There is no perf difference between INS SIMD to SIMD and ZIP on Arm uArches but preferring the INS alternative has a drawback on all uArches as ZIP being a three operand instruction can be used to tie the result to the return register whereas INS would require an fmov. As such just update the test file for now. gcc/testsuite/ChangeLog: PR target/112375 * gcc.target/aarch64/vget_set_lane_1.c: Update test output.
