[Bug target/114028] New: [14] RISC-V rv64gcv_zvl256b: miscompile at -O3

[patrick at rivosinc dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114028

            Bug ID: 114028
           Summary: [14] RISC-V rv64gcv_zvl256b: miscompile at -O3
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

Testcase:
int a, d = 55003;
long c, h;
long e = 1;
char g;
short i;

int main() {
  g = 0;
  for (; g < 16; g += 1) {
    d |= c;
    short l = d;
    i = l < 0 || a >> 4 ? d : a;
    h = i - 8L;
    e &= h;
  }

  if (e == 1)
    return 0;
  else
    return 1;
}


Commands:
> /scratch/tc-testing/tc-feb-20/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc 
> -march=rv64gcv_zvl256b -O3 red.c -o red.out
> QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true 
> /scratch/tc-testing/tc-feb-20-llvm/build/bin/qemu-riscv64 user-config.out
> echo $?
1

> /scratch/tc-testing/tc-feb-20/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc 
> -march=rv64gcv_zvl256b -O2 red.c -o red.out
> QEMU_CPU=rv64,vlen=256,v=true,vext_spec=v1.0,zve32f=true,zve64f=true 
> /scratch/tc-testing/tc-feb-20-llvm/build/bin/qemu-riscv64 red.out
> echo $?
0

Discovered/tested using 61ab046a327 (not bisected)
Found using fuzzer