https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113682
--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Mathias Stearn from comment #5)
> Do you know if that applies to any cores that support x86_64? I checked
> Agner Fog's tables, and only very very old cores (P4 era) had high
> reciprocal throughput, but even then it was less than latency. It looks like
> all AMD cores and intel cores newer than ivy bridge (ie everything from the
> last 10 years) are able to execute multiple CMOVs per cycle (reciprocal
> throughput < 1). From what I can see, it looks like bad CMOV was a
> particular problem of the Pentium 4 and Prescott cores, and possibly PPro,
> but I don't see the numbers for it. I don't think any of those cores should
> have an impact on the default cost model in 2024.
/* X86_TUNE_ONE_IF_CONV_INSNS: Restrict a number of cmov insns in
if-converted sequence to one. */
DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
| m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
| m_ZHAOXIN | m_GENERIC)
So it looks like it is the low power atom cores which still have this issue.
Tremont is from 2021 so you can't say those cores should not impact default
cost models ...
