https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113695
Bug ID: 113695
Summary: RISC-V: Sources with different EEW must use different
registers
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: juzhe.zhong at rivai dot ai
Target Milestone: ---
As this PR in LLVM, https://github.com/llvm/llvm-project/issues/80099
RVV ISA:
A vector register cannot be used to provide source operands with more than one
EEW for a single instruction. A
mask register source is considered to have EEW=1 for this constraint. An
encoding that would result in the
same vector register being read with two or more different EEWs, including when
the vector register appears at
different positions within two or more vector register groups, is reserved.
#include <stdint.h>
#include <riscv_vector.h>
void foo(vuint64m2_t colidx, uint32_t* base_addr, size_t vl) {
vuint32m1_t values =
__riscv_vget_v_u32m2_u32m1(__riscv_vreinterpret_v_u64m2_u32m2 (colidx), 0);
__riscv_vsuxei64_v_u32m1(base_addr, colidx, values, vl);
}
foo:
vsetvli zero,a1,e32,m1,ta,ma
vsuxei64.v v8,(a0),v8
ret
It is incorrect those 2 input operand with different EEW should not be the same
register (v8).
Current GCC RTL machine description and constraint can not allow us to fix it.
Even though it is a bug, I think we can only revisit it in GCC-15.
