[Bug tree-optimization/113677] Missing `VEC_PERM_EXPR <{a, CST}, CST, {0, 1, 2, ...}>` optimization

[pinskia at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113677

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|x86_64                      |x86_64 aarch64

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Here is another example, using 64/128 on aarch64:
```
#define vect64 __attribute__((vector_size(8) ))
#define vect128 __attribute__((vector_size(16) ))

vect128 unsigned int f(vect64 unsigned int a)
{
  vect64 unsigned int zero={0, 0};
  return __builtin_shufflevector (a, zero, 0, 1, 2, 3);
}
```

We get:
```
f:
        movi    v31.4s, 0
        fmov    d0, d0
        zip1    v0.2d, v0.2d, v31.2d
```

This should just produce the `fmov` for little-endian and `mov/ins` for
big-endian.

Note for this part of the issue the aarch64 back-end represents zip using
UNSPEC where it could use VEC_CONCAT instead. And it would do the correct thing
there ...