https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113231
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Summary|x86_64 use MMX instructions |x86_64 uses SSE
|for simple shift operations |instructions for `*mem <<=
| |const` at -Os
Last reconfirmed| |2024-01-04
Keywords| |missed-optimization
Status|UNCONFIRMED |NEW
Ever confirmed|0 |1
--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
> Registers conversion cost: 0
In this case we start off with:
```
(insn 6 3 0 2 (parallel [
(set (mem:SI (reg/v/f:DI 100 [ iD.2766 ]) [1 *i_4(D)+0 S4 A32])
(ashift:SI (mem:SI (reg/v/f:DI 100 [ iD.2766 ]) [1 *i_4(D)+0 S4
A32])
(const_int 1 [0x1])))
(clobber (reg:CC 17 flags))
]) "/app/example.cpp":3:8 911 {*ashlsi3_1}
(expr_list:REG_DEAD (reg/v/f:DI 100 [ iD.2766 ])
(expr_list:REG_UNUSED (reg:CC 17 flags)
(nil))))
```
Which has 0 registers usage but then STV does not take into account the need
for the load/store for SSE registers.
