https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104914
--- Comment #24 from GCC Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by YunQiang Su <s...@gcc.gnu.org>: https://gcc.gnu.org/g:65d4b32dee2508f5bcdd999a132332cd46cf8a4d commit r14-6905-g65d4b32dee2508f5bcdd999a132332cd46cf8a4d Author: YunQiang Su <s...@gcc.gnu.org> Date: Sat Dec 30 00:17:52 2023 +0800 MIPS: Add pattern insqisi_extended and inshisi_extended This match pattern allows combination (zero_extract:DI 8, 24, QI) with an sign-extend to 32bit INS instruction on TARGET_64BIT. For SI mode, if the sign-bit is modified by bitops, we will need a sign-extend operation. Since 32bit INS instruction can be sure that result is sign-extended, and the QImode src register is safe for INS, too. (insn 19 18 20 2 (set (zero_extract:DI (reg/v:DI 200 [ val ]) (const_int 8 [0x8]) (const_int 24 [0x18])) (subreg:DI (reg:QI 205) 0)) "../xx.c":7:29 -1 (nil)) (insn 20 19 23 2 (set (reg/v:DI 200 [ val ]) (sign_extend:DI (subreg:SI (reg/v:DI 200 [ val ]) 0))) "../xx.c":7:29 -1 (nil)) Combine try to merge them to: (insn 20 19 23 2 (set (reg/v:DI 200 [ val ]) (sign_extend:DI (ior:SI (and:SI (subreg:SI (reg/v:DI 200 [ val ]) 0) (const_int 16777215 [0xffffff])) (ashift:SI (subreg:SI (reg:QI 205 [ MEM[(const unsigned char *)buf_8(D) + 3B] ]) 0) (const_int 24 [0x18]))))) "../xx.c":7:29 18 {*insv_extended} (expr_list:REG_DEAD (reg:QI 205 [ MEM[(const unsigned char *)buf_8(D) + 3B] ]) (nil))) And do similarly for 16/16 pair: (insn 13 12 14 2 (set (zero_extract:DI (reg/v:DI 198 [ val ]) (const_int 16 [0x10]) (const_int 16 [0x10])) (subreg:DI (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) 0)) "xx.c":5:30 286 {*insvdi} (expr_list:REG_DEAD (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) (nil))) (insn 14 13 17 2 (set (reg/v:DI 198 [ val ]) (sign_extend:DI (subreg:SI (reg/v:DI 198 [ val ]) 0))) "xx.c":5:30 241 {extendsidi2} (nil)) ------------> (insn 14 13 17 2 (set (reg/v:DI 198 [ val ]) (sign_extend:DI (ior:SI (ashift:SI (subreg:SI (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) 0) (const_int 16 [0x10])) (zero_extend:SI (subreg:HI (reg/v:DI 198 [ val ]) 0))))) "xx.c":5:30 284 {*inshisi_extended} (expr_list:REG_DEAD (reg:HI 201 [ MEM[(const short unsigned int *)buf_6(D) + 2B] ]) (nil))) Let's accept these patterns, and set the cost to 1 instruction. gcc PR rtl-optimization/104914 * config/mips/mips.md (insqisi_extended): New patterns. (inshisi_extended): Ditto. gcc/testsuite * gcc.target/mips/pr104914.c: New test.
