https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113076
Edwin Lu <ewlu at rivosinc dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Summary|[14] RISC-V: |[14] RISC-V:
|gfortran.dg/dec_io_1.f90 |gfortran.dg/dec_io_1.f90
|runtime error after |runtime error after
|r14-4971-g0beb1611754 |r14-4972-g8aa47713701
--- Comment #2 from Edwin Lu <ewlu at rivosinc dot com> ---
(In reply to Richard Biener from comment #1)
> The bisection is highly suspicious since that's a x86 specific change that
> doesn't affect riscv.
Sorry about that I linked the wrong commit. I bisected it down to
r14-4972-g8aa47713701
8aa47713701b1f1878b81169852269a299272e87 is the first bad commit
commit 8aa47713701b1f1878b81169852269a299272e87
Author: Vladimir N. Makarov <vmaka...@redhat.com>
Date: Fri Oct 27 08:28:24 2023 -0400
[RA]: Add cost calculation for reg equivalence invariants
My recent patch improving cost calculation for pseudos with equivalence
resulted in failure of gcc.target/arm/eliminate.c on aarch64. This patch
fixes this failure.
gcc/ChangeLog:
* ira-costs.cc: (get_equiv_regno, calculate_equiv_gains):
Process reg equivalence invariants.
gcc/ira-costs.cc | 4 ++++
1 file changed, 4 insertions(+)
