[Bug target/113014] RISC-V: Redundant zeroing instructions in reduction due to r14-3998-g6223ea766daf7c

[juzhe.zhong at rivai dot ai via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113014

--- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Richard S has a late combine PASS which is going to be merged in GCC-14.

Since we generate this following RTL int split1:

(insn 48 24 49 5 (set (reg:SI 149)
        (const_int 0 [0])) -1
     (nil))

(insn 49 48 50 5 (set (reg:RVVM1SI 148)
        (if_then_else:RVVM1SI (unspec:RVVMF32BI [
                    (const_vector:RVVMF32BI [
                            (const_int 1 [0x1])
                            repeat [
                                (const_int 0 [0])
                            ]
                        ])
                    (const_int 1 [0x1])
                    (const_int 2 [0x2]) repeated x2
                    (const_int 0 [0])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (vec_duplicate:RVVM1SI (reg:SI 149))
            (unspec:RVVM1SI [
                    (reg:SI 0 zero)
                ] UNSPEC_VUNDEF))) -1
     (nil))

I suspect late-combine PASS can combine it into:

(insn 49 48 50 5 (set (reg:RVVM1SI 148)
        (if_then_else:RVVM1SI (unspec:RVVMF32BI [
                    (const_vector:RVVMF32BI [
                            (const_int 1 [0x1])
                            repeat [
                                (const_int 0 [0])
                            ]
                        ])
                    (const_int 1 [0x1])
                    (const_int 2 [0x2]) repeated x2
                    (const_int 0 [0])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (CONST_VECTOR: 0)
            (unspec:RVVM1SI [
                    (reg:SI 0 zero)
                ] UNSPEC_VUNDEF))) -1
     (nil))

that is: combine

(set(reg0) (0)) and (vec_duplicate:reg0) 

into:

(CONST_VECTOR:0)

after split1 by late-combine PASS.

I am not sure.

Hi,Robin. Could you confirm it for me ?