[Bug target/112932] [14] RISC-V rv64gcv_zvl256b vector: Incorrect behavior with nested loop array writing

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112932

--- Comment #1 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:9363d91956931bb28735bed97035b9ec965c850f

commit r14-6354-g9363d91956931bb28735bed97035b9ec965c850f
Author: Juzhe-Zhong <juzhe.zh...@rivai.ai>
Date:   Sat Dec 9 16:31:53 2023 +0800

    RISC-V: Fix VLS mode movmiaslign bug

    PR112932 let me notice there is a bug of current VLS mode misalign pattern.
    Adapt it same as VLA mode.

    Commited as it is obvious fix.

            PR target/112932

    gcc/ChangeLog:

            * config/riscv/vector.md (movmisalign<mode>): Fix VLSmode bugs.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/vls/misalign-1.c: Ditto.
            * gcc.target/riscv/rvv/autovec/pr112932.c: New test.