[Bug middle-end/112872] [14 Regression] RISCV ICE: in store_integral_bit_field, at expmed.cc:1049 with -03 rv64gcv_zvl1024b --param=riscv-autovec-preference=fixed-vlmax

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112872

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rd...@gcc.gnu.org>:

https://gcc.gnu.org/g:056cce412862f8d9b56a40dfbcbc3f9fa7f92883

commit r14-6211-g056cce412862f8d9b56a40dfbcbc3f9fa7f92883
Author: Robin Dapp <rd...@ventanamicro.com>
Date:   Tue Dec 5 15:24:12 2023 +0100

    RISC-V: Add vec_init expander for masks [PR112854].

    PR112854 shows a problem on rv32 with zvl1024b.  During the course of
    expand_constructor we try to overlay/subreg a 64-element mask by a
    scalar (Pmode) register.  This works for zvl512b and its maximum of
    32 elements but fails for rv32 and 64 elements.

    To circumvent this this patch adds a vec_init expander for vector masks
    by initializing a QImode vector and comparing that against 0.

    gcc/ChangeLog:

            PR target/112854
            PR target/112872

            * config/riscv/autovec.md (vec_init<mode>qi): New expander.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr112854.c: New test.
            * gcc.target/riscv/rvv/autovec/pr112872.c: New test.