https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112598
--- Comment #12 from Li Pan <pan2.li at intel dot com> --- Hi Robin, Do you have any ideas about the possible fix for this issue? The x86 backend has one workaround for this issue as below. https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=dbf8ab449417aa24669f6ccf50be8c17f8c1278e But unfortunately not suitable for riscv after a quick try because of the below define_insn: (define_insn "@pred_store<mode>" [(set (match_operand:V 0 "memory_operand" "+m") // "=m" here for x86 SSE. Given current stage of GCC, I am not quite sure if we need to fix it in the backend (Or bypass it) or from the middle end.
