https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112694
--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Pan Li <pa...@gcc.gnu.org>: https://gcc.gnu.org/g:aea337cf740ec33022f3cabfa7dd4333d5ba78ee commit r14-5825-gaea337cf740ec33022f3cabfa7dd4333d5ba78ee Author: Juzhe-Zhong <juzhe.zh...@rivai.ai> Date: Fri Nov 24 16:34:28 2023 +0800 RISC-V: Fix inconsistency among all vectorization hooks This patches 200+ ICEs exposed by testing with rv64gc_zve64d. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112694 The rootcause is we disallow poly (1,1) size vectorization in preferred_simd_mode. with this following code: - if (TARGET_MIN_VLEN < 128 && TARGET_MAX_LMUL < RVV_M2) - return word_mode; However, we allow poly (1,1) size in hook: TARGET_VECTORIZE_RELATED_MODE TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES And also enables it in all vectorization patterns. I was adding this into preferred_simd_mode because poly (1,1) size mode will cause ICE in can_duplicate_and_interleave_p. So, the alternative approach we need to block poly (1,1) size in both TARGET_VECTORIZE_RELATED_MODE and TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES hooks and all vectorization patterns. which is ugly approach and too much codes change. Now, after investivation, I find it's nice that loop vectorizer can automatically block poly (1,1) size vector in interleave vectorization with this commit: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=730909fa858bd691095bc23655077aa13b7941a9 So, we don't need to worry about ICE in interleave vectorization and allow poly (1,1) size vector in vectorization which fixes 200+ ICEs in zve64d march. PR target/112694 gcc/ChangeLog: * config/riscv/riscv-v.cc (preferred_simd_mode): Allow poly_int (1,1) vectors. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112694-1.c: New test.
