https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112431
--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> --- My colleague Lehua takes this response to support this feature.
[Bug c/112431] RISC-V GCC-15 feature: Support register overlap on widen RVV instructions
juzhe.zhong at rivai dot ai via Gcc-bugs Tue, 07 Nov 2023 16:16:52 -0800
- [Bug c/112431] New: RISC-V GCC-... juzhe.zhong at rivai dot ai via Gcc-bugs
- [Bug c/112431] RISC-V GCC-... juzhe.zhong at rivai dot ai via Gcc-bugs
- [Bug c/112431] RISC-V GCC-... juzhe.zhong at rivai dot ai via Gcc-bugs
- [Bug c/112431] RISC-V GCC-... kito at gcc dot gnu.org via Gcc-bugs
- [Bug c/112431] RISC-V GCC-... pinskia at gcc dot gnu.org via Gcc-bugs
- [Bug target/112431] RISC-V... cvs-commit at gcc dot gnu.org via Gcc-bugs
- [Bug target/112431] RISC-V... cvs-commit at gcc dot gnu.org via Gcc-bugs
- [Bug target/112431] RISC-V... cvs-commit at gcc dot gnu.org via Gcc-bugs
- [Bug target/112431] RISC-V... cvs-commit at gcc dot gnu.org via Gcc-bugs
- [Bug target/112431] RISC-V... cvs-commit at gcc dot gnu.org via Gcc-bugs
