https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112361
--- Comment #6 from Robin Dapp <rdapp at gcc dot gnu.org> ---
So "before" we created
vect__3.12_55 = MEM <vector(16) float> [(float *)vectp_a.10_53];
vect__ifc__43.13_57 = VEC_COND_EXPR <mask__24.9_52, vect__3.12_55, { 0.0,
0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 }>;
// _ifc__43 = _24 ? _3 : 0.0;
stmp__44.14_58 = BIT_FIELD_REF <vect__ifc__43.13_57, 32, 0>;
stmp__44.14_59 = r3_29 + stmp__44.14_58;
...
in vect_expand_fold_left.
Now, as intended, there is no VEC_COND anymore and we just create the bit-field
reduction over the unmasked vector.
We could refrain from creating the COND_OP in the first place as Jakub
mentioned (I guess we know already in if-conv that we shouldn't), re-insert a
VEC_COND or create a COND_OP chain (instead of an OP chain) in
vect_expand_fold_left by passing it the mask (and is_cond_op).
Having several COND_OPs here might make analysis of subsequent passes more
difficult?
