https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101955
--- Comment #9 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Roger Sayle <sa...@gcc.gnu.org>: https://gcc.gnu.org/g:a3da9adeb457d4f01c4e695a9621f90c2e2a5e68 commit r14-5014-ga3da9adeb457d4f01c4e695a9621f90c2e2a5e68 Author: Roger Sayle <ro...@nextmovesoftware.com> Date: Mon Oct 30 16:21:28 2023 +0000 ARC: Convert (signed<<31)>>31 to -(signed&1) without barrel shifter. This patch optimizes PR middle-end/101955 for the ARC backend. On ARC CPUs with a barrel shifter, using two shifts is optimal as: asl_s r0,r0,31 asr_s r0,r0,31 but without a barrel shifter, GCC -O2 -mcpu=em currently generates: and r2,r0,1 ror r2,r2 add.f 0,r2,r2 sbc r0,r0,r0 with this patch, we now generate the smaller, faster and non-flags clobbering: bmsk_s r0,r0,0 neg_s r0,r0 2023-10-30 Roger Sayle <ro...@nextmovesoftware.com> gcc/ChangeLog PR middle-end/101955 * config/arc/arc.md (*extvsi_1_0): New define_insn_and_split to convert sign extract of the least significant bit into an AND $1 then a NEG when !TARGET_BARREL_SHIFTER. gcc/testsuite/ChangeLog PR middle-end/101955 * gcc.target/arc/pr101955.c: New test case.
