https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111677
Alex Coplan <acoplan at gcc dot gnu.org> changed:
What |Removed |Added
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CC| |rsandifo at gcc dot gnu.org
--- Comment #13 from Alex Coplan <acoplan at gcc dot gnu.org> ---
The problem seems to be this code in aarch64_process_components:
while (regno != last_regno)
{
bool frame_related_p = aarch64_emit_cfi_for_reg_p (regno);
machine_mode mode = aarch64_reg_save_mode (regno);
rtx reg = gen_rtx_REG (mode, regno);
poly_int64 offset = frame.reg_offset[regno];
if (frame_pointer_needed)
offset -= frame.bytes_below_hard_fp;
rtx addr = plus_constant (Pmode, ptr_reg, offset);
rtx mem = gen_frame_mem (mode, addr);
which emits a TFmode mem with offset 512, which is out of range for TFmode (so
we later ICE with an unrecognisable insn). Presumably this just needs tweaking
to emit a new base anchor in the case of large offsets like this. It looks
like the code in aarch64_save_callee_saves already does this.
