https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111926
--- Comment #2 from Kito Cheng <kito at gcc dot gnu.org> --- Forgot to mention, personally I love idea to simplify code gen, I could imagine that's definitely an optimization for specific uarch :)
[Bug target/111926] RISC-V: Use vsetvl insn replace csrr vlenb insn
kito at gcc dot gnu.org via Gcc-bugs Sun, 22 Oct 2023 21:25:09 -0700
- [Bug target/111926] New: RISC-V: U... lehua.ding at rivai dot ai via Gcc-bugs
- [Bug target/111926] RISC-V: U... kito at gcc dot gnu.org via Gcc-bugs
- [Bug target/111926] RISC-V: U... kito at gcc dot gnu.org via Gcc-bugs
- [Bug target/111926] RISC-V: U... lehua.ding at rivai dot ai via Gcc-bugs
- [Bug target/111926] RISC-V: U... pinskia at gcc dot gnu.org via Gcc-bugs
