https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111645
--- Comment #4 from Steven Munroe <munroesj at gcc dot gnu.org> --- Actually shift/rotate intrinsic: ,vec_rl, vec_rlmi, vec_rlnm, vec_sl, vec_sr, vec_sra Support vector __int128 as required for the PowerISA 3.1 POWER vector shift/rotate quadword instructions But: vec_sld, vec_sldb, vec_sldw, vec_sll, vec_slo, vec_srdb, vec_srl, vec_sro Do not. There is no obvious reason for this inconstancy as the target instructions are effectively 128/256-bit operations returning a 128-bit result.The type of the inputs is incidental to the operation. Any restrictions imposed by the original Altivec.h PIM was broken long ago by VSX and PowerISA 2.07. Net: the Power Vector Intrinsic Programming Reference and the compilers should support the vector __int128 type for any instruction where it makes sense as a input or result.
