https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111594
--- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> --- (In reply to JuzheZhong from comment #3) > (In reply to Andrew Pinski from comment #1) > > The SVE one was added with r12-4402-g62b505a4d5fc89: > > ``` > > /* Detect simplication for a conditional reduction where > > > > a = mask1 ? b : 0 > > c = mask2 ? d + a : d > > > > is turned into > > > > c = mask1 && mask2 ? d + b : d. */ > > (simplify > > (IFN_COND_ADD @0 @1 (vec_cond @2 @3 integer_zerop) @1) > > (IFN_COND_ADD (bit_and @0 @2) @1 @3 @1)) > > ``` > > Most likely should do the similar thing for IFN_COND_LEN_ADD too. > > Hi, I saw ARM SVE failed to fold VEC_COND + COND_ADD into COND_ADD on > float vector since it can't satisfy integer_zerop. > > Is is reasonable the same optimization should also work for float vector ? I suspect it would only be valid if `!HONOR_NANS (type) && !HONOR_SIGNED_ZEROS (type)` is true. So it could use (match on) zerop instead but would need to check the above conditional too.
