[Bug target/111259] [14 Regression] ICE: RTL check: expected code 'reg', have 'subreg' in rhs_regno, at rtl.h:1934 during riscv64 build

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111259

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Patrick O'Neill <pone...@gcc.gnu.org>:

https://gcc.gnu.org/g:d7b6020276a843e97f6135259b4ab3b53a5850e2

commit r14-4044-gd7b6020276a843e97f6135259b4ab3b53a5850e2
Author: Fei Gao <gao...@eswincomputing.com>
Date:   Fri Sep 15 01:20:08 2023 +0000

    fix PR 111259 invalid zcmp mov predicate.

    The code changes are from Palmer.

    root cause:
    In a gcc build with --enable-checking=yes, REGNO (op) checks
    rtx code and expected code 'reg'. so a rtx with 'subreg' causes
    an internal compiler error.

    solution:
    Restrict predicate to allow 'reg' only.

    gcc/ChangeLog:

            * config/riscv/predicates.md: Restrict predicate
            to allow 'reg' only.
    Reviewed-by: Palmer Dabbelt <pal...@rivosinc.com>
    Acked-by: Palmer Dabbelt <pal...@rivosinc.com>