[Bug middle-end/111395] RISC-V Vector Fortran: ICE in get_avl_or_vl_reg (vsetvl pass)

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:53ad1bd520759580b9a5cc590a81a1a30b9e2e28

commit r14-3979-g53ad1bd520759580b9a5cc590a81a1a30b9e2e28
Author: Juzhe-Zhong <juzhe.zh...@rivai.ai>
Date:   Thu Sep 14 15:52:13 2023 +0800

    RISC-V: Fix ICE in get_avl_or_vl_reg

    update v1 -> v2: Add available fortran compiler check in rvv-fortran.exp.

    This patch fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111395 ICE

    update v2 -> v3: Remove redundant format.

            PR target/111395

    gcc/ChangeLog:

            * config/riscv/riscv-vsetvl.cc (avl_info::operator==): Fix ICE.
            (vector_insn_info::global_merge): Ditto.
            (vector_insn_info::get_avl_or_vl_reg): Ditto.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/fortran/pr111395.f90: New test.
            * gcc.target/riscv/rvv/rvv-fortran.exp: New test.