[Bug target/105928] [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least)

[wilco at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105928

Wilco <wilco at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |wilco at gcc dot gnu.org
           Assignee|unassigned at gcc dot gnu.org      |wilco at gcc dot gnu.org

--- Comment #2 from Wilco <wilco at gcc dot gnu.org> ---
Shifted logical operations are single cycle on all recent cores.