https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111318
Bug ID: 111318
Summary: RISC-V: Redundant vsetvl instructions
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: lehua.ding at rivai dot ai
Target Milestone: ---
The next two vsetvl instructions in assembly should be removed. Because the
vadd instruction is calculated in vlmax length, but where it is used only the
first avl, we can change the vl of the vadd to the avl of the instruction being
used.
C Code:
#include <riscv_vector.h>
void foo1 (int32_t* restrict a, int32_t* restrict b, int32_t *restrict c, int
n)
{
for (int i = 0; i < n; i += 1)
c[i] = a[i] + b[i];
}
Assembly Code:
foo1:
ble a3,zero,.L5
.L3:
vsetvli a5,a3,e32,m2,ta,ma
vle32.v v4,0(a0)
vle32.v v2,0(a1)
vsetvli a6,zero,e32,m2,ta,ma
slli a4,a5,2
vadd.vv v2,v2,v4
sub a3,a3,a5
vsetvli zero,a5,e32,m2,ta,ma
vse32.v v2,0(a2)
add a0,a0,a4
add a1,a1,a4
add a2,a2,a4
bne a3,zero,.L3
.L5:
ret
https://godbolt.org/z/jzWjK6EM9
