https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111246
--- Comment #10 from David Edelsohn <dje at gcc dot gnu.org> ---
If I compile your testcase with either GCC 11.3 or GCC trunk, GCC produces
P1:
.LFB1:
.cfi_startproc
.localentry P1,1
pld 9,.LANCHOR0+8@pcrel
sync
lwz 9,0(9)
cmpw 0,9,9 <*** compare
bne- 0,$+4 <*** branch conditional
isync <*** isync
pld 10,.LANCHOR0@pcrel
li 8,1
stw 8,0(10)
pld 10,.LANCHOR0+16@pcrel
stw 9,0(10)
blr
which contains the branch conditional that should satisfy the processor memory
model. I'm not seeing the unconditional branch that you see in your example.
Your link to Compiler Explorer code generated by Clang also shows a branch
conditional
P1: # @P1
.quad .Lfunc_begin1
.quad .TOC.@tocbase
.quad 0
.Lfunc_begin1:
addis 3, 2, y@toc@ha
ld 3, y@toc@l(3)
sync
li 5, 1
lwz 3, 0(3)
cmpd 7, 3, 3 <*** compare
bne- 7, .+4 <*** branch conditional
isync <*** isync
What is generating or parsing or interpreting the unconditional branch shown in
your pasted code?
