[Bug middle-end/110994] RISC-V Fortran: Illegal instruction ICE with scalable autovec

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:9890f377013cf1e4f5b9fab8a7287a5380dade1f

commit r14-3177-g9890f377013cf1e4f5b9fab8a7287a5380dade1f
Author: Juzhe-Zhong <juzhe.zh...@rivai.ai>
Date:   Sat Aug 12 10:30:02 2023 +0800

    RISC-V: Add TAREGT_VECTOR check into VLS modes

    This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994

    This is caused VLS modes incorrect codes int register allocation.

    The original case trigger the ICE is fortran code but I can reproduce
    with a C code.

    gcc/ChangeLog:

            PR target/110994
            * config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Add TARGET_VETOR.

    gcc/testsuite/ChangeLog:

            PR target/110994
            * gcc.target/riscv/rvv/autovec/vls/pr110994.c: New test.