https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110985
Bug ID: 110985
Summary: RISC-V: Incorrect code gen for RVV VLS
Product: gcc
Version: 14.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: pan2.li at intel dot com
Target Milestone: ---
Given we have the below sample code.
#include <stdint.h>
typedef int16_t vnx16i __attribute__ ((vector_size (32)));
void
foo (int16_t *__restrict out)
{
vnx16i v = {15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0};
*(vnx16i *) out = v;
}
It will generate below incorrect asm when compile with "-march=rv64gcv -O3
--param=riscv-autovec-preference=fixed-vlmax".
foo:
ret
In fact it may be something similar to below assembly code.
foo:
vsetivli zero, 16, e16, m2, ta, ma
vid.v v8
vrsub.vi v8, v8, 15
vse16.v v8, (a0)
ret
