https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88873
--- Comment #9 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Roger Sayle <sa...@gcc.gnu.org>: https://gcc.gnu.org/g:097106972f243ddcbddbbddd9a6bcc076f58b453 commit r14-2668-g097106972f243ddcbddbbddd9a6bcc076f58b453 Author: Roger Sayle <ro...@nextmovesoftware.com> Date: Thu Jul 20 09:23:11 2023 +0100 i386: More TImode parameter passing improvements. This patch is the next piece of a solution to the x86_64 ABI issues in PR 88873. This splits the *concat<mode><dwi>3_3 define_insn_and_split into two patterns, a TARGET_64BIT *concatditi3_3 and a !TARGET_64BIT *concatsidi3_3. This allows us to add an additional alternative to the the 64-bit version, enabling the register allocator to perform this operation using SSE registers, which is implemented/split after reload using vec_concatv2di. To demonstrate the improvement, the test case from PR88873: typedef struct { double x, y; } s_t; s_t foo (s_t a, s_t b, s_t c) { return (s_t){ __builtin_fma(a.x, b.x, c.x), __builtin_fma (a.y, b.y, c.y) }; } when compiled with -O2 -march=cascadelake, currently generates: foo: vmovq %xmm2, -56(%rsp) movq -56(%rsp), %rax vmovq %xmm3, -48(%rsp) vmovq %xmm4, -40(%rsp) movq -48(%rsp), %rcx vmovq %xmm5, -32(%rsp) vmovq %rax, %xmm6 movq -40(%rsp), %rax movq -32(%rsp), %rsi vpinsrq $1, %rcx, %xmm6, %xmm6 vmovq %xmm0, -24(%rsp) vmovq %rax, %xmm7 vmovq %xmm1, -16(%rsp) vmovapd %xmm6, %xmm2 vpinsrq $1, %rsi, %xmm7, %xmm7 vfmadd132pd -24(%rsp), %xmm7, %xmm2 vmovapd %xmm2, -56(%rsp) vmovsd -48(%rsp), %xmm1 vmovsd -56(%rsp), %xmm0 ret with this change, we avoid many of the reloads via memory, foo: vpunpcklqdq %xmm3, %xmm2, %xmm7 vpunpcklqdq %xmm1, %xmm0, %xmm6 vpunpcklqdq %xmm5, %xmm4, %xmm2 vmovdqa %xmm7, -24(%rsp) vmovdqa %xmm6, %xmm1 movq -16(%rsp), %rax vpinsrq $1, %rax, %xmm7, %xmm4 vmovapd %xmm4, %xmm6 vfmadd132pd %xmm1, %xmm2, %xmm6 vmovapd %xmm6, -24(%rsp) vmovsd -16(%rsp), %xmm1 vmovsd -24(%rsp), %xmm0 ret 2023-07-20 Roger Sayle <ro...@nextmovesoftware.com> gcc/ChangeLog * config/i386/i386-expand.cc (ix86_expand_move): Don't call force_reg, to use SUBREG rather than create a new pseudo when inserting DFmode fields into TImode with insvti_{high,low}part. * config/i386/i386.md (*concat<mode><dwi>3_3): Split into two define_insn_and_split... (*concatditi3_3): 64-bit implementation. Provide alternative that allows register allocation to use SSE registers that is split into vec_concatv2di after reload. (*concatsidi3_3): 32-bit implementation. gcc/testsuite/ChangeLog * gcc.target/i386/pr88873.c: New test case.
