[Bug target/110299] RISC-V: ICE when build RVV intrinsic widen with "-march=rv32gc_zve64d -mabi=ilp32d", both GCC 14 and 13.

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110299

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <pa...@gcc.gnu.org>:

https://gcc.gnu.org/g:26bb67fc4d4b4bbefe298e21c965d41bb412eeb6

commit r14-1946-g26bb67fc4d4b4bbefe298e21c965d41bb412eeb6
Author: Pan Li <pan2...@intel.com>
Date:   Sun Jun 18 23:07:53 2023 +0800

    RISC-V: Bugfix for RVV widenning reduction in ZVE32/64

    The rvv widdening reduction has 3 different patterns for zve128+, zve64
    and zve32. They take the same iterator with different attributions.
    However, we need the generated function code_for_reduc (code, mode1,
mode2).
    The implementation of code_for_reduc may look like below.

    code_for_reduc (code, mode1, mode2)
    {
      if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
        return CODE_FOR_pred_reduc_maxvnx1hfvnx16hf; // ZVE128+

      if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
        return CODE_FOR_pred_reduc_maxvnx1hfvnx8hf;  // ZVE64

      if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)
        return CODE_FOR_pred_reduc_maxvnx1hfvnx4hf;  // ZVE32
    }

    Thus there will be a problem here. For example zve32, we will have
    code_for_reduc (max, VNx1HF, VNx1HF) which will return the code of
    the ZVE128+ instead of the ZVE32 logically.

    This patch will merge the 3 patterns into pattern, and pass both the
    input_vector and the ret_vector of code_for_reduc. For example, ZVE32
    will be code_for_reduc (max, VNx1HF, VNx2HF), then the correct code of
ZVE32
    will be returned as expectation.

    Please note both GCC 13 and 14 are impacted by this issue.

    Signed-off-by: Pan Li <pan2...@intel.com>
    Co-Authored by: Juzhe-Zhong <juzhe.zh...@rivai.ai>

    gcc/ChangeLog:

            PR target/110299
            * config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
            modes.
            * config/riscv/vector-iterators.md: Remove VWLMUL1, VWLMUL1_ZVE64,
            VWLMUL1_ZVE32, VI_ZVE64, VI_ZVE32, VWI, VWI_ZVE64, VWI_ZVE32,
            VF_ZVE63 and VF_ZVE32.
            * config/riscv/vector.md
            (@pred_widen_reduc_plus<v_su><mode><vwlmul1>): Removed.
            (@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve64>): Ditto.
            (@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve32>): Ditto.
            (@pred_widen_reduc_plus<order><mode><vwlmul1>): Ditto.
            (@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>): Ditto.
            (@pred_widen_reduc_plus<v_su><VQI:mode><VHI_LMUL1:mode>): New
pattern.
            (@pred_widen_reduc_plus<v_su><VHI:mode><VSI_LMUL1:mode>): Ditto.
            (@pred_widen_reduc_plus<v_su><VSI:mode><VDI_LMUL1:mode>): Ditto.
            (@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>): Ditto.
            (@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>): Ditto.

    gcc/testsuite/ChangeLog:

            PR target/110299
            * gcc.target/riscv/rvv/base/pr110299-1.c: New test.
            * gcc.target/riscv/rvv/base/pr110299-1.h: New test.
            * gcc.target/riscv/rvv/base/pr110299-2.c: New test.
            * gcc.target/riscv/rvv/base/pr110299-2.h: New test.
            * gcc.target/riscv/rvv/base/pr110299-3.c: New test.
            * gcc.target/riscv/rvv/base/pr110299-3.h: New test.
            * gcc.target/riscv/rvv/base/pr110299-4.c: New test.
            * gcc.target/riscv/rvv/base/pr110299-4.h: New test.