https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82931
--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The releases/gcc-12 branch has been updated by Georg-Johann Lay <g...@gcc.gnu.org>: https://gcc.gnu.org/g:4d39f68b891ed2ac7aca5ef24119f50976b84c22 commit r12-9654-g4d39f68b891ed2ac7aca5ef24119f50976b84c22 Author: Georg-Johann Lay <a...@gjlay.de> Date: Thu May 25 19:02:34 2023 +0200 target/82931: Make a pattern more generic to match more bit-transfers. There is already a pattern in avr.md that matches single-bit transfers from one register to another one, but it only handled bit 0 of 8-bit registers. This change makes that pattern more generic so it matches more of similar single-bit transfers. gcc/ PR target/82931 * config/avr/avr.md (*movbitqi.0): Rename to *movbit<mode>.0-6. Handle any bit position and use mode QISI. * config/avr/avr.cc (avr_rtx_costs_1) [IOR]: Return a cost of 2 insns for bit-transfer of respective style. gcc/testsuite/ PR target/82931 * gcc.target/avr/pr82931.c: New test.
