[Bug target/99195] Optimise away vec_concat of 64-bit AdvancedSIMD operations with zeroes in aarch64

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99195

--- Comment #13 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkac...@gcc.gnu.org>:

https://gcc.gnu.org/g:3ed5677bb61b334a2d01c769859cdd3279e12a07

commit r14-654-g3ed5677bb61b334a2d01c769859cdd3279e12a07
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date:   Wed May 10 12:00:17 2023 +0100

    [PATCH] aarch64: PR target/99195 annotate simple permutation patterns for
vec-concat-zero

    Another straightforward patch annotating patterns for the zip1, zip2, uzp1,
uzp2, rev* instructions, plus tests.
    Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

    gcc/ChangeLog:

            PR target/99195
            * config/aarch64/aarch64-simd.md
(aarch64_<PERMUTE:perm_insn><mode>):
            Rename to...
            (aarch64_<PERMUTE:perm_insn><mode><vczle><vczbe>): ... This.
            (aarch64_rev<REVERSE:rev_op><mode>): Rename to...
            (aarch64_rev<REVERSE:rev_op><mode><vczle><vczbe>): ... This.

    gcc/testsuite/ChangeLog:

            PR target/99195
            * gcc.target/aarch64/simd/pr99195_1.c: Add tests for zip and rev
            intrinsics.