https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109592
Bug ID: 109592
Summary: Failure to recognize shifts as sign/zero extension
Product: gcc
Version: 13.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: rtl-optimization
Assignee: unassigned at gcc dot gnu.org
Reporter: law at gcc dot gnu.org
Target Milestone: ---
This is a trivial sign extension:
int sextb32(int x)
{ return (x << 24) >> 24; }
Yet on RV64 with ZBB enabled we get:
sextb32:
slliw a0,a0,24 # 6 [c=4 l=4] ashlsi3
sraiw a0,a0,24 # 13 [c=8 l=4] *ashrsi3_extend
ret # 21 [c=0 l=4] simple_return
We actually get a good form to optimize in simplify_binary_operation_1:
> #0 simplify_context::simplify_binary_operation (this=0x7fffffffda68,
> code=ASHIFTRT, mode=E_SImode, op0=0x7fffea11eb40, op1=0x7fffea009610) at
> /home/jlaw/riscv-persist/ventana/gcc/gcc/simplify-rtx.cc:2558
> 2558 gcc_assert (GET_RTX_CLASS (code) != RTX_COMPARE);
> (gdb) p code
> $24 = ASHIFTRT
> (gdb) p mode
> $25 = E_SImode
> (gdb) p debug_rtx (op0)
> (ashift:SI (subreg/s/u:SI (reg/v:DI 74 [ x ]) 0)
> (const_int 24 [0x18]))
> $26 = void
> (gdb) p debug_rtx (op1)
> (const_int 24 [0x18])
> $27 = void
So that's (ashiftrt (ashift (object) 24) 24), ie sign extension.
I suspect if we fix simplify_binary_operation_1 then we'll see this get
simplified by fwprop. I also suspect we could construct a zero extension
variant.
