https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109347
Bug ID: 109347
Summary: [lra] Spill failure for architecture without CC
Product: gcc
Version: 12.2.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: middle-end
Assignee: unassigned at gcc dot gnu.org
Reporter: piggynl at outlook dot com
Target Milestone: ---
Created attachment 54791
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=54791&action=edit
Reproduce for riscv64
For all architectures without condition code, when all registers are in use,
gcc fails to perform a spill.
mips64 and riscv64 are failing with certain code.
For example, the codes for mips64 and riscv64 reproducing the bug are in
attachments.
The expected behavior is generating a spill asm sequence before the `if` block
and a restore sequence after, so it will be a free register in the `if` block.
gcc is failing an assertion error with the examples. With a release build, gcc
falls into an infinity loop.
The assertion fails in lra.c:
if (e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun))
{
/* We already made the edge no-critical in ira.c::ira */
lra_assert (!EDGE_CRITICAL_P (e));
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
rtx_insn *tmp = BB_HEAD (e->dest);
if (LABEL_P (tmp))
The assertion was introduced in e3b3b59683c1.
