https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109244
--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Kito Cheng <k...@gcc.gnu.org>: https://gcc.gnu.org/g:cd0c433e5faba9a18f64881cd761a53a530aa798 commit r13-6823-gcd0c433e5faba9a18f64881cd761a53a530aa798 Author: Ju-Zhe Zhong <juzhe.zh...@rivai.ai> Date: Wed Mar 22 10:49:56 2023 +0800 RISC-V: Fix LRA issue for LMUL < 1 vector spillings [PR109244] In order to decrease the memory traffic, we don't use whole register load/store for the LMUL less than 1 and mask mode, so those case will require one extra general purpose register for setting up VL register, but it's not allowed during LRA process, so we defined few special move patterns used for LRA, which will defer the expansion after LRA. gcc/ChangeLog: PR target/109244 * config/riscv/riscv-protos.h (emit_vlmax_vsetvl): Define as global. (emit_vlmax_op): Ditto. * config/riscv/riscv-v.cc (get_sew): New function. (emit_vlmax_vsetvl): Adapt function. (emit_pred_op): Ditto. (emit_vlmax_op): Ditto. (emit_nonvlmax_op): Ditto. (legitimize_move): Fix LRA ICE. (gen_no_side_effects_vsetvl_rtx): Adapt function. * config/riscv/vector.md (@mov<V_FRACT:mode><P:mode>_lra): New pattern. (@mov<VB:mode><P:mode>_lra): Ditto. (*mov<V_FRACT:mode><P:mode>_lra): Ditto. (*mov<VB:mode><P:mode>_lra): Ditto. gcc/testsuite/ChangeLog: PR target/109244 * g++.target/riscv/rvv/base/pr109244.C: New test. * gcc.target/riscv/rvv/base/binop_vv_constraint-4.c: Adapt testcase. * gcc.target/riscv/rvv/base/binop_vv_constraint-6.c: Ditto. * gcc.target/riscv/rvv/base/binop_vx_constraint-127.c: Ditto. * gcc.target/riscv/rvv/base/spill-1.c: Ditto. * gcc.target/riscv/rvv/base/spill-2.c: Ditto. * gcc.target/riscv/rvv/base/spill-3.c: Ditto. * gcc.target/riscv/rvv/base/spill-5.c: Ditto. * gcc.target/riscv/rvv/base/spill-7.c: Ditto. * g++.target/riscv/rvv/base/bug-18.C: New test. * gcc.target/riscv/rvv/base/merge_constraint-3.c: New test. * gcc.target/riscv/rvv/base/merge_constraint-4.c: New test.
