https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85048
--- Comment #9 from Hongtao.liu <crazylht at gmail dot com> ---
With the patch, we can generate optimized code expect for those 16 {u,}qq
cases, since the ABI doesn't support 1024-bit vector.
1 file changed, 16 insertions(+), 2 deletions(-)
gcc/config/i386/sse.md | 18 ++++++++++++++++--
modified gcc/config/i386/sse.md
@@ -8014,8 +8014,9 @@ (define_expand "fixuns_trunc<mode><sseintvecmodelower>2"
(match_operand:VF1 1 "register_operand")]
"TARGET_SSE2"
{
- if (<MODE>mode == V16SFmode)
- emit_insn (gen_ufix_truncv16sfv16si2 (operands[0],
+ /* AVX512 support vcvttps2udq for all 128/256/512-bit vectors. */
+ if (<MODE>mode == V16SFmode || TARGET_AVX512VL)
+ emit_insn (gen_ufix_trunc<mode><sseintvecmodelower>2 (operands[0],
operands[1]));
else
{
@@ -8413,6 +8414,12 @@ (define_insn "*float<floatunssuffix>v2div2sf2_mask_1"
(set_attr "prefix" "evex")
(set_attr "mode" "V4SF")])
+(define_expand "floatuns<si2dfmodelower><mode>2"
+ [(set (match_operand:VF2_512_256VL 0 "register_operand")
+ (unsigned_float:VF2_512_256VL
+ (match_operand:<si2dfmode> 1 "nonimmediate_operand")))]
+ "TARGET_AVX512F")
+
(define_insn "ufloat<si2dfmodelower><mode>2<mask_name>"
[(set (match_operand:VF2_512_256VL 0 "register_operand" "=v")
(unsigned_float:VF2_512_256VL
@@ -8694,6 +8701,13 @@ (define_insn "fix_truncv4dfv4si2<mask_name>"
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
+
+/* The standard pattern name is fixuns_truncmn2. */
+(define_expand "fixuns_truncv4dfv4si2"
+ [(set (match_operand:V4SI 0 "register_operand")
+ (unsigned_fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand")))]
+ "TARGET_AVX512VL && TARGET_AVX512F")
+
(define_insn "ufix_truncv4dfv4si2<mask_name>"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unsigned_fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand"
"vm")))]
