https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109093
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Ever confirmed|0 |1
Last reconfirmed| |2023-03-13
Status|UNCONFIRMED |NEW
--- Comment #6 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
#c3 looks very similarly, though have just looked at assembly:
pushq %rbp
.LCFI0:
movl $36, %r11d
movl $7, %eax
vpxor %xmm0, %xmm0, %xmm0
movq %rsp, %rbp
.LCFI1:
pushq %r15
pushq %r14
pushq %r13
pushq %r12
.LCFI2:
movl $127, %r13d
pushq %rbx
.LCFI3:
leaq -48(%rsp), %rsi
...
.L5:
vmovdqa %xmm0, (%rsi)
so again, %rbp after movq %rsp, %rbp is correctly 16-byte aligned, then 5
registers are pushed, so (%rsp & 15) == 8, %rsi is set to %rsp - 48 and an
aligned store to that spot
segfaults because (%rsi & 15) == 8.
And similarly #c4:
pushq %rbp
.LCFI0:
movabsq $434041037028460038, %rax
movq %rsp, %rbp
.LCFI1:
pushq %rbx
.LCFI2:
movq %rax, -41(%rsp)
movb $6, -33(%rsp)
cmpl $-6, (%rdi)
jne .L84
movl $2, %r8d
leaq -32(%rsp), %rcx
...
vmovdqa %xmm1, (%rcx)
vmovdqa %xmm0, 16(%rcx)
H.J., could you please have a look? Thanks.
