[Bug target/108172] [13 Regression] ICE in emit_move_multi_word, at expr.cc:4087 since r13-4616-g2cba118e538ba0

[jakub at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108172

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org,
                   |                            |ktkachov at gcc dot gnu.org,
                   |                            |rearnsha at gcc dot gnu.org

--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I think the problem is that while movv8hf and movv4hf expanders have just
TARGET_FLOAT
condition, movv2hf has TARGET_FLOAT && TARGET_SIMD_F16INST condition.
But aarch64_classify_vector_mode enables V2HFmode whenever TARGET_FLOAT.

So, IMHO (but what do I know about aarch64), either we need:
--- gcc/config/aarch64/aarch64.cc.jj    2022-12-14 20:30:40.492312699 +0100
+++ gcc/config/aarch64/aarch64.cc       2023-01-06 13:17:53.475412480 +0100
@@ -3634,8 +3634,9 @@ aarch64_classify_vector_mode (machine_mo
     case E_V8BFmode:
     case E_V4SFmode:
     case E_V2DFmode:
-    case E_V2HFmode:
       return TARGET_FLOAT ? VEC_ADVSIMD : 0;
+    case E_V2HFmode:
+      return TARGET_FLOAT && TARGET_SIMD_F16INST ? VEC_ADVSIMD : 0;

     default:
       return 0;
(which fixes the ICE but haven't tested it in any way further) or movv2hf needs
to work even for plain TARGET_FLOAT && !TARGET_SIMD_F16INST.