https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104921
--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> --- (define_insn "aarch64_bfmlal<bt>_lane<q>v4sf" [(set (match_operand:V4SF 0 "register_operand" "=w") (plus: V4SF (match_operand:V4SF 1 "register_operand" "0") (unspec:V4SF [(match_operand:V8BF 2 "register_operand" "w") (match_operand:VBF 3 "register_operand" "w") (match_operand:SI 4 "const_int_operand" "n")] BF_MLA)))] "TARGET_BF16_SIMD" { operands[4] = aarch64_endian_lane_rtx (<MODE>mode, INTVAL (operands[4])); return "bfmlal<bt>\\t%0.4s, %2.8h, %3.h[%4]"; } [(set_attr "type" "neon_fp_mla_s_scalar_q")] ) Operand 3 should have be: (match_operand:VBF 3 "register_operand" "x")