https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108031
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Component|target |middle-end
Target|riscv*-*-* |riscv*-*-* aarch64-*-*
Last reconfirmed| |2022-12-09
Ever confirmed|0 |1
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
On aarch64 and -O2 -fno-section-anchors -march=armv8.1-a we get:
adrp x1, s
mov w2, 1
add x1, x1, :lo12:s
ldadd w2, w0, [x1]
adrp x1, s+4
add x1, x1, :lo12:s+4
ldadd w2, w2, [x1]
add w0, w0, w2
On riscv32 with -O2 -msmall-data-limit=0 (note I wish -G was used on riscv like
every other target so I don't have to remember what the riscv specific option
name is):
lui a5,%hi(.LANCHOR0)
addi a5,a5,%lo(.LANCHOR0)
li a4,1
amoadd.w a0,a4,0(a5)
addi a5,a5,4
amoadd.w a3,a4,0(a5)
add a0,a0,a3
